List of Publications

  1. H.Hirata and A.Nunome. ``Performance Evaluation on Parallel Speculation-Based Construction of a Binary Search Tree.'' International Journal of Networked and Distributed Computing (IJNDC), International Association for Computer and Information Science (ACIS), Springer Nature, 24 pages, DOI:10.1007/s44227-023-00013-w (Open Accerss), November 2023.
  2. A.Nunome and H.Hirata. ``Adaptive Parameter Tuning for Constructing Storage Tiers in an Autonomous Distributed Storage System.'' International Journal of Networked and Distributed Computing (IJNDC), International Association for Computer and Information Science (ACIS), Atrantice Press (Springer Nature), Vol.10, no.1-2, 10 pages, DOI:10.1007/s44227-022-00004-3 (Open Access), December 2022.
  3. H.Hirata and A.Nunome. ``Parallel Binary Search Tree Construction Inspired by Thread-Level Speculation.'' Proceedings of the 23rd International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2022-Summer), ACIS, pp.74-81, July 2022.
  4. A.Nunome and H.Hirata. ``Enhancing the Performance of an Autonomous Distributed Storage System in a Large-Scale Network.'' Proceedings of the 23rd International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2022-Summer), ACIS, pp.87-94, July 2022.
  5. H.Hirata and A.Nunome. ``Reducing the Repairing Penalty on Misspeculation in Thread-Level Speculation.'' Proceedings of the 8th International Virtual Conference on Applied Computing & Information Technology (ACIT 2021), ACIS and ACM, pp.39-45, June 2021.
  6. A.Nunome and H.Hirata. ``An Adaptive Tiering Scheme for an Autonomous Distributed Storage System.'' Proceedings of the 8th International Virtual Conference on Applied Computing & Information Technology (ACIT 2021), ACIS and ACM, pp.62-68, June 2021.
  7. H.Hirata and A.Nunome. ``A Modified Parallel Heapsort Algorithm.'' International Journal of Software Innovation (IJSI), IGI Global, Vol.8, No.3, pp.1-18, July-September 2020.
  8. H.Hirata and A.Nunome. ``Decoupling Computation and Result Write-Back for Thread-Level Parallelization.'' International Journal of Software Innovation (IJSI), IGI Global, Vol.8, No.3, pp.19-34, July-September 2020.
  9. A.Nunome and H.Hirata. ``Performance Evaluation of Data Migration Policies for a Distributed Storage System with Dynamic Tiering.'' International Journal of Networked and Distributed Computing (IJNDC), Atlantis Press, Vol.8, No.1, pp.1-8, December 2019.
  10. K.Nakanishi, T.Hochin, H.Nomiya and H.Hirata. ``Multi-Dimensional Indexing System Considering Distributions of Sub-indexes and Data.'' International Journal of Networked and Distributed Computing (IJNDC), Atlantis Press, Vol.8, No.1, pp.25-33, December 2019.
  11. D.Matsunaga, A.Nunome and H.Hirata. ``Shelving a Code Block for Thread-Level Speculation.'' Proceedings of the 20th International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2019), ACIS and IEEE, pp.427-434, July 2019.
  12. H.Kitano, A.Nunome and H.Hirata. ``Performance Evaluation of Parallel Heapsort Programs.'' Proceedings of the 20th International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2019), ACIS and IEEE, pp.435-442, July 2019.
  13. A.Nunome and H.Hirata. ``An Improvement of Migration Efficiency in a Distributed Storage System with Dynamic Tiering.'' Proceedings of the 20th International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2019), ACIS and IEEE, pp.455-460, July 2019.
  14. K.Nakanishi, T.Hochin, H.Nomiya and H.Hirata. ``Improvement of Multi-Dimensional Indexing System for Multimedia Big Data.'' Proceedings of the 20th International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2019), ACIS and IEEE, pp.449-454, July 2019.
  15. H.Yamasaki, A.Nunome and H.Hirata. ``Parallelizing the Construction of a k-Dimensional Tree.'' Proceedings of the 3rd International Conference on Big Data, Cloud Computing, and Data Science & Engineering (BCD 2018), ACIS and IEEE, pp.33-40, July 2018.
  16. A.Nunome and H.Hirata. ``A Data Migration Scheme Considering Node Reliability for an Autonomous Distributed Storage System.'' Proceedings of the 5th International Conference on Computational Science/Intelligence and Applied Informatics (CSII 2018), ACIS, pp.160-165, July 2018. (Best Paper Award)
  17. K.Fujisawa, A.Nunome, K.Shibayama and H.Hirata. ``A Software Implementation of Speculative Memory.'' Proceedings of the 18th International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2017), ACIS and IEEE, pp.437-443, June 2017.
  18. S.Ichii, S.Hayashi, A.Nunome, H.Hirata and K.Shibayama. ``Performance Evaluation of Delayed-Committing Transactional Memory.'' Proceedings of the 18th International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2017), ACIS and IEEE, pp.445-451, June 2017.
  19. S.Shimano, A.Nunome, Y.Yokoi, K.Shibayama and H.Hirata. ``An Autonomous Configuration Scheme of Storage Tiers for Distributed File System.'' Proceedings of the 18th International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2017), ACIS and IEEE, pp.453-458, June 2017. (Best Student Presenter Award)
  20. H.Hirata, A.Nunome and K.Shibayama. ``Speculative Memory: An Architectural Support for Explicit Speculations in Multithreaded Programming.'' Proceedings of the 15th International Conference on Computer and Information Science (ICIS 2015), ACIS and IEEE, pp.715-721, June 2016.
  21. A.Nunome, H.Hirata and K.Shibayama. ``An Interval Control Method for Status Propagation in an Autonomous Distributed Storage System.'' Proceedings of the 15th International Conference on Computer and Information Science (ICIS 2015), ACIS and IEEE, pp.723-728, June 2016.
  22. Y.Shoji, A.Nunome, H.Hirata and K.Shibayama. ``A Large-Scale Speculation for the Thread-Level Parallelization.'' International Journal of Computer and Information Science (IJCIS), ACIS, Vol.17, No.1, pp.24-32, January-March 2016.
  23. S.Ichii, S.Tashiro, A.Nunome, H.Hirata and K.Shibayama. ``Hardware Transactional Memory with Delayed Committing.'' Proceedings of the 3rd International Conference on Applied Computing and Information Technology (ACIT 2015), ACIS, pp. 161-168, July 2015.
  24. Y.Shoji, A.Nunome, H.Hirata and K.Shibayama. ``A Large-Scale Speculation for the Thread-Level Parallelization.'' Proceedings of the 3rd International Conference on Applied Computing and Information Technology (ACIT 2015), ACIS, pp. 169-175, July 2015.
  25. S. Shimano, A.Nunome, H.Hirata and K.Shibayama. ``An Information Propagation Scheme for an Autonomous Distributed Storage System in iSCSI Environment.'' Proceedings of the 3rd International Conference on Applied Computing and Information Technology (ACIT 2015), ACIS, pp. 149-154, July 2015.
  26. A.Nunome, H.Hirata and K.Shibayama. ``A Distributed Storage System with Dynamic Tiering for iSCSI Environment.'' International Journal of Networked and Distributed Computing (IJNDC), ACIS, Vol.3, No.1, pp.42-50, January 2015.
  27. S.Ichii, A.Nunome, H.Hirata and K.Shibayama. ``A Lazy-Updating Snoop Cache Protocol for Transactional Memory.'' Proceedings of the International Conference on Software Engineering Research, Management and Applications (SERA 2014), ACIS, pp. 636-643, August-September 2014.
  28. A.Nunome, H.Hirata and K.Shibayama. ``A Distributed Storage System with Dynamic Tiering for iSCSI Environment.'' Proceedings of the International Conference on Software Engineering Research, Management and Applications (SERA 2014), ACIS, pp. 644-649, August-September 2014.
  29. S.Ichii, A.Nunome, H.Hirata and K.Shibayama. ``A Lazy-Updating Snoop Cache Protocol for Transactional Memory.'' International Journal of Computer and Information Science (IJCIS), ACIS, Vol.15, No.1, pp. 31-40, June 2014.
  30. K.Nakatsukasa, A.Nunome, H.Hirata and K.Shibayama. ``A Microprocessor Architecture Enhanced to Detect Return Address Corruption.'' IEICE Transactions, Vol.J97-D, No.3, pp.614-624, March 2014. (in Japanese)
  31. H.Hirata, T.Fujii, K.Fuji, K.Morita, A.Nunome and K.Shibayama. ``A Memory Renaming Mechanism for a Thread-Level Speculation on a Multiprocessor.'' Proceedings of Forum on Information Technology (FIT2012), Vol.1, pp.31-34, September 2012. (in Japanese)
  32. K.Akasaka, A.Nunome, H.Hirata and K.Shibayama. ``Database Query Scheduling to Improve the Response Time in an Electronic Commerce Site.'' Proceedings of Forum on Information Technology (FIT2011), Vol.1, pp.113-116, September 2011. (in Japanese)
  33. K.Nakatsukasa, T.Yamada, A.Nunome, H.Hirata and K.Shibayama. ``Processor Architecture Featured with a Precise Detection Mechanism of Stack Smashing Attacks.'' Proceedings of Forum on Information Technology (FIT2011), Vol.1, pp.63-66, September 2011. (in Japanese)
  34. A.Nunome, H.Hirata and K.Shibayama. ``A Multicast Filtering Ethernet Switch for Network Authentication in IPv6 Networks.'' Proceedings of Forum on Information Technology (FIT2011), Vol.4, pp.1-4, September 2011. (in Japanese)
  35. A.Nunome, H.Hirata, M.Fukuzawa and K.Shibayama. ``Development of an E-learning Back-end System for Code Assessment in Elementary Programming Practice." SIGUCCS Fall 2010 Conference, ACM, pp.181-186, October 2010.
  36. K.Morita, A.Nunome, H.Hirata and K.Shibayama. ``Classification of Inter-Thread Dependencies for Thread-Level Parallelization.'' Proceedings of Forum on Information Technology (FIT2010), Vol.1, pp.81-86, September 2010. (in Japanese)
  37. H.Hirata, T.Yamada, A.Nunome and K.Shibayama. ``Precise Detection of Procedure Calling/Returning through Machine Instruction-Level Monitoring.'' Proceedings of Forum on Information Technology (FIT2010), Vol.1, pp.87-90, September 2010. (in Japanese)
  38. A.Nunome, H.Hirata and K.Shibayama. ``An Ethernet Switch with Two-Level Broadcast Domain for Network Authentication.'' IEICE Transactions, Vol.J88-D-I, No.4, pp.908-911, April 2005. (in Japanese)
  39. A.Nunome, H.Hirata, H.Niimi and K.Shibayama. ``Performance Evaluation of Dynamic Load Balancing Scheme with Load Prediction Mechanism Using the Load Growing Acceleration for Massively Parallel Computers.'' Systems and Computers in Japan, Wiley, Vol.35, No.11, pp.69-79, November 2004.
  40. S.Yamamura, T.Kadota, H.Hirata, H.Niimi, and K.Shibayama. ``Evaluation of a Data Preload Mechanism for a Linked List Structure.'' Systems and Computers in Japan, Wiley, Vol.33, No.3, pp.21-30, March 2002.
  41. A.Nunome, H.Hirata, H.Niimi and K.Shibayama. ``Performance Evaluation of Dynamic Load Balancing Scheme with Load Prediction Mechanism Using the Load Growing Asseleration for Massively Parallel Computer.'' IEICE Transactions, Vol.J84-D-I, No.11, pp.1532-1541, November 2001. (in Japanese)
  42. A.Nunome, H.Hirata, H.Niimi and K.Shibayama. ``An Improvement of Dynamic Load Balancing Scheme with Load Prediction Mechanism for Massively Parallel Computers.'' IPSJ Transactions, Vol.42, No.5, pp.1282-1285, May 2001. (in Japanese)
  43. S.Yamamura, T.Kadota, H.Hirata, H.Niimi, and K.Shibayama. ``An Evaluation of a Data Preload Mechanism for a Linked List Structure.'' IEICE Transactions, Vol.J84-D-I, No.2, pp.136-145, February 2001. (in Japanese)
  44. A.Nunome, H.Hirata, H.Niimi and K.Shibayama. ``Performance Evaluation of Dynamic Load Balancing Scheme with Load Prediction Mechanism Using the Load Growing Accelaration for Massively Parallel Computers.'' IEICE Transactions, Vol.J83-D-I, No.9, pp.936-945, September 2000. (in Japanese)
  45. S.Yamamura, T.Kadota, H.Hirata, H.Niimi, and K.Shibayama. ``An Evaluation of a Data Preload Mechanism for a Linked List Structure.'' IEICE Transactions, Vol.J84-D-I, No.2, pp.136-145, September 2000. (in Japanese)
  46. A.Nunome, H.Hirata, H.Niimi and K.Shibayama. ``Dynamic Load Balancing Scheme Considering the Load Growing Rate for Massively Parallel Computers.'' IEICE Transactions, Vol.J83-D-I, No.9, pp.936-945, September 2000. (in Japanese)
  47. S.Yamamura, H.Hirata, H.Niimi, and K.Shibayama. ``A Data Prefetching Mechanism for a Linked List Structure.'' Proceedings of the Joint Symposium on Parallel Processing (JSPP) 2000, IPSJ and IEICE, pp.115-122, May 2000. (in Japanese)
  48. T.Motokawa, S.Yamamura, A.Nunome, H.Hirata, H.Niimi and K.Shibayama. ``Parallel Execution of Loop Iterations by Speculative Traversal on Recursive Data Structures.'' The Special Interest Groupe Notes on Computer Architecture, IPSJ, Vol.2000, No.1, pp.1-6, January 2000. (in Japanese)
  49. H.Hirata, A.Okumura, Y.Shibata, H.Niimi and K.Shibayama. ``Performance Comparisons of Instruction Cache Configurations and Instruction Fetch Schemes for a Multithreaded Processor or a 1-Chip Multiprocessor.'' IEICE Transactions, Vol.J81-D-I, No.6, pp.718-727, June 1998. (in Japanese)
  50. K.Amatsu, H.Hirata, H.Niimi and K.Shibayama. ``Studies of Hierarchical Thread Scheduling for Distributed Memory Parallel Processors.'' IEICE Transactions, Vol.J80-D-I, No.7, pp.615-623, July 1997. (in Japanese)
  51. T.Onoye, T.Masaki, I.Shirakawa, H.Hirata, K.Kimura, S.Asahara and T.Sagishima. ``High-Level Synthesis of a Multithreaded Processor for Image Generation.'' IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E78-A, No.3, pp.322-330, March 1995.
  52. T.Onoye, T.Masaki, H.Hirata, K.Kimura, S.Asahara, T.Sagishima, I.Shirakawa, S.Tsukiyama and S.Shinoda. ``High-Level Synthesis of A Multithreaded Processor Dedicated to Image Generation: Design and Simulation.'' 1994 European Simulation Multiconference,Barcelona, Spain, pp.948-953, June 1994.
  53. T.Sagishima, K.Kimura, H.Hirata, T.Kiyohara, S.Asahara, T.Onoye and I.Shirakawa. ``Multithreaded Processor for Image Generation.'' 1994 IEEE International Symposium on Circuits and Systems, London, England, Vol.4, pp.231-234, May 1994.
  54. K.Kimura, H.Hirata, T.Kiyohara, S.Asahara, T.Sagishima, T.Onoye and I.Shirakawa. ``Evaluation Method of Microarchitecture for Multithreaded Processor.'' IEEE International Symposium on Industrial Electronics, Santiago, Chile, pp.53-58, May 1994.
  55. H.Hirata, K.Kimura, S.Nagamine, T.Nishizawa and T.Sagishima. ``An Elementary Processor Architecture with Parallel Instruction Issuing from Multiple Threads.'' IPSJ Transactions, Vol.34, No.4, pp.595-605, April 1993. (in Japanese)
  56. H.Hirata, K.Kimura, S.Nagamine, Y.Mochizuki, A.Nishimura, Y.Nakase and T.Nishizawa. ``An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads.'' Proceedings of the 19th Annual International Symposium on Computer Architecture, ACM, pp.136-145, May 1992.
  57. H.Hirata, Y.Mochizuki, A.Nishimura, Y.Nakase and T.Nishizawa. ``A Multithreaded Processor Architecture with Simultaneous Instruction Issuing.'' Journal of Supercomputer, Springer-Verlag, Vol.IX, No.3, pp.23-39, May 1992.
  58. H.Hirata, Y.Mochizuki, A.Nishimura, Y.Nakase and T.Nishizawa. ``A Multithreaded Processor Architecture with Simultaneous Instruction Issuing.'' Proceedings of the International Symposium on Supercomputing(ISS'91), Fukuoka, Japan, Kyushu University, pp.87-96, November 1991.
  59. H.Hirata, K.Shibayama and H.Hagiwara. ``Process Management of a Logic Programming Language-Oriented Parallel Machine KPR.'' IPSJ Transactions, Vol.31, No.3, pp.361-372, March 1990. (in Japanese)
  60. K.Shibayama, H.Kage, Y.Kawakura, M.Yamamoto, H.Hirata, Y.Kanoh and H.Hagiwara. ``Parallel Processings of a Logic Programming Language-Oriented Parallel Machine KPR.'' IPSJ Transactions, Vol.30, No.12, pp.1573-1583, December 1989. (in Japanese)
  61. K.Shibayama, M.Yamamoto, H.Hirata, Y.Kanoh, T.Sanetoh and H.Hagiwara. ``KPR: A Logic Programming Language-Oriented Parallel Machine.'' Lecture Notes in Computer Science 315, Springer-Verlag, pp.113-131, August 1988.
Go Back Go back to Hirata's Home Page

Last Updated: November 9, 2023