KUE-CHIP2 (Kyoto University Education Chip 2) is an 8-bit microprocessor developed as a teaching aid for computer education at universities and other institutions. KUE-CHIP2 has an extremely simple architecture and a basic instruction set.
Using the KUE-CHIP2 educational board, it is possible to observe and change the state of registers and memory during execution while executing the program one clock cycle or one instruction at a time.
KUE-CHIP2 educational boards are manufactured and sold by ASTEM. Follow ASTEM Home Page for details.
[IMPORTANT NOTICE] KUE-CHIP2 is now out of distribution as of the end of March 2025.
All excerpts are from the "KUE-CHIP2 Educational Board Reference Manual"
| ACC | Accumulator |
| IX | Index Register |
| d | Immediate Address |
| [d] | Absolute Address (Code Region) |
| (d) | Absolute Address (Data Region) |
| [IX+d] | Indexed Address (Code Region) |
| (IX+d) | Indexed Address (Data Region) |
| {ea} | Entire Address Mode |
| {reg} | Register Address Mode |
| {imm} | Immediate Address Mode |
| {ma} | Memory Reference Address Mode |
| ACC | IX | d | [d] | (d) | [IX+d] | (IX+d) | |
| {ea} | ◯ | ◯ | ◯ | ◯ | ◯ | ◯ | ◯ |
| {reg} | ◯ | ◯ | ⨯ | ⨯ | ⨯ | ⨯ | ⨯ |
| {imm} | ⨯ | ⨯ | ◯ | ⨯ | ⨯ | ⨯ | ⨯ |
| {ma} | ⨯ | ⨯ | ⨯ | ◯ | ◯ | ◯ | ◯ |
| Mnemonic | Address Mode | Instruction Function | |
|---|---|---|---|
|
HLT
NOP |
Halt
No OPeration | ||
|
IN
OUT |
INput
OUTput | ||
|
SCF
RCF |
Set Carry Flag
Reset Carry Flag | ||
|
LD
ST |
{reg},{ea}
{reg},{ma} |
LoaD
STore | |
|
ADD
ADC SUB SBC CMP AND OR EOR |
{reg},{ea}
{reg},{ea} {reg},{ea} {reg},{ea} {reg},{ea} {reg},{ea} {reg},{ea} {reg},{ea} |
ADD
ADd with Carry SUBtract SuBtract with Carry CoMPare AND OR Exclusive OR | |
|
Ssm
Rsm |
{reg}
{reg} |
Shift
Rotate | |
| sm |
RA
LA RL LL |
Right Arithmetically
Left Arithmerically Right Logically Left Logically | |
| Bcc | {imm} | Branch | |
| cc |
A
VF NZ Z ZP N P ZN NI NO NC C GE LT GT LE |
Always
on oVerFlow on Not Zero on Zero on Zero or Positive on Negative on Positive on Zero or Negative on No Input on No Output on No Carry on Carry on Greater than or Equal on Less Than on Greater Than on Less than or Equal | |
| Abbreviation | Instruction code (First) | B' (Second) | Instruction Function Overview | |
|---|---|---|---|---|
| NOP |
0 0 0 0 0 - - -
| ⨯ | No OPeration | |
| HLT |
0 0 0 0 1 - - -
| ⨯ | HaLT | Halt |
0 1 0 1 - - - -
| ⨯ | Unused (HLT) | ||
| OUT |
0 0 0 1 0 - - -
| ⨯ | OUTput | (ACC)→OBUF |
| IN |
0 0 0 1 1 - - -
| ⨯ | INput | (IBUF)→ACC |
| RCF |
0 0 1 0 0 - - -
| ⨯ | Reset CF | 0→CF |
| SCF |
0 0 1 0 1 - - -
| ⨯ | Set CF | 1→CF |
| Bcc |
0 0 1 1 cc
| ⦾ | Branch cc | If the condition is satisfied, B'→PC |
| Ssm |
0 1 0 0 A 0 sm
| ⨯ | Shift sm |
(A)→shift, rotate→A Overflowing bit→CF |
| Rsm |
0 1 0 0 A 1 sm
| ⨯ | Rotate sm | |
| LD |
0 1 1 0 A B
| ◯ | LoaD | (B)→A |
| ST |
0 1 1 1 A B
| ⦾ | STore | (A)→B |
| SBC |
1 0 0 0 A B
| ◯ | SuBtract with Carry | (A)-(B)-CF→A |
| ADC |
1 0 0 1 A B
| ◯ | ADd with Carry | (A)+(B)+CF→A |
| SUB |
1 0 1 0 A B
| ◯ | SUBtract | (A)-(B)→A |
| ADD |
1 0 1 1 A B
| ◯ | ADD | (A)+(B)→A |
| EOR |
1 1 0 0 A B
| ◯ | Exclusive OR | (A)⨁(B)→A |
| OR |
1 1 0 1 A B
| ◯ | OR | (A)∨(B)→A |
| AND |
1 1 1 0 A B
| ◯ | AND | (A)∧(B)→A |
| CMP |
1 1 1 1 A B
| ◯ | CoMPare | (A)-(B) |
0: ACC1: IX000: ACC001: IX01-: d (Immediate Address)100: [d] (Absolute Address)101: (d) (Absolute Address)110: [IX+d] (Indexed Address)111: (IX+d) (Indexed Address)| Abbreviation | Condition Code | Function Overview |
|---|---|---|
| A | 0 0 0 0 |
Always |
| VF | 1 0 0 0 |
on oVerFlow |
| NZ | 0 0 0 1 |
on Not Zero |
| Z | 1 0 0 1 |
on Zero |
| ZP | 0 0 1 0 |
on Zero or Positive |
| N | 1 0 1 0 |
on Negative |
| P | 0 0 1 1 |
on Positive |
| ZN | 1 0 1 1 |
on Zero or Negative |
| NI | 0 1 0 0 |
on No Input |
| NO | 1 1 0 0 |
on No Output |
| NC | 0 1 0 1 |
on Not Carry |
| C | 1 1 0 1 |
on Carry |
| GE | 0 1 1 0 |
on Greater than or Equal |
| LT | 1 1 1 0 |
on Less Than |
| GT | 0 1 1 1 |
on Greater Than |
| LE | 1 1 1 1 |
on Less than or Equal |
| Abbreviation | Condition Code | Function Overview |
|---|---|---|
| RA | 0 0 |
Right Arithmetically |
| LA | 0 1 |
Left Arithmetically |
| RL | 1 0 |
Right Logically |
| LL | 1 1 |
Left Logically |
| Mnemonic | Outline | Bit operations |
|---|---|---|
| SRA | Shift Right Arithmetically |  |
| SLA† | Shift Left Arithmetically |  |
| SRL | Shift Right Logically |  |
| SLL† | Shift Left Logically | |
| RRA | Rotate Right Arithmetically |  |
| RLA | Rotate Left Arithmetically |  |
| RRL | Rotate Right Logically |  |
| RLL | Rotate Left Logically |  |
† SLA and SLL instructions have different flag states after execution. (See Flag functions for details)
CF: Carry Flag, VF: oVerflow Flag, NF: Negative Flag, ZF: Zero Flag
| Mnemonic | Outline of instruction functions | Effect on Execution† | Post-execution status‡ | ||||||
|---|---|---|---|---|---|---|---|---|---|
| CF | VF | NF | ZF | CF | VF | NF | ZF | ||
| NOP | No OPeration | - | - | - | - | - | - | - | - |
| HLT | HaLT | - | - | - | - | - | - | - | - |
| OUT | OUTput | - | - | - | - | - | - | - | - |
| IN | INput | - | - | - | - | - | - | - | - |
| RCF | Reset Carry Flag | - | - | - | - | 0 | - | - | - |
| SCF | Set Carry Flag | - | - | - | - | 1 | - | - | - |
| SRA | Shift Right Arithmetically | - | - | - | - | b0 | 0 | N | Z |
| SLA | Shift Left Arithmetically | - | - | - | - | b7 | V | N | Z |
| SRL | Shift Right Logically | - | - | - | - | b0 | 0 | N | Z |
| SLL | Shift Left Logically | - | - | - | - | b7 | 0 | N | Z |
| RRA | Rotate Right Arithmetically | b7 | - | - | - | b0 | 0 | N | Z |
| RLA | Rotate Left Arithmetically | b0 | - | - | - | b7 | V | N | Z |
| RRL | Rotate Right Logically | - | - | - | - | b0 | 0 | N | Z |
| RLL | Rotate Left Logically | - | - | - | - | b7 | 0 | N | Z |
| LD | LoaD | - | - | - | - | - | - | - | - |
| ST | STore | - | - | - | - | - | - | - | - |
| SBC | SuBtract with Carry | c | - | - | - | C | V | N | Z |
| ADC | ADd with Carry | c | - | - | - | C | V | N | Z |
| SUB | SUBtract | - | - | - | - | - | V | N | Z |
| ADD | ADD | - | - | - | - | - | V | N | Z |
| EOR | Exclusive OR | - | - | - | - | - | 0 | N | Z |
| OR | OR | - | - | - | - | - | 0 | N | Z |
| AND | AND | - | - | - | - | - | 0 | N | Z |
| CMP | CoMPare | - | - | - | - | - | V | N | Z |
| BA | Branch Always | - | - | - | - | - | - | - | - |
| BVF | Branch on oVerFlow | - | VF | - | - | - | - | - | - |
| BNZ | Branch on Not Zero | - | - | - | ZF |
- | - | - | - |
| BZ | Branch on Zero | - | - | - | ZF | - | - | - | - |
| BZP | Branch on Zero or Positive | - | - | NF | - | - | - | - | - |
| BN | Branch on Negative | - | - | NF | - | - | - | - | - |
| BP | Branch on Positive | - | - | NF∨ZF |
- | - | - | - | |
| BZN | Branch on Zero or Negative | - | - | NF∨ZF | - | - | - | - | |
| BNI | Branch on No Input | - | - | - | - | - | - | - | - |
| BNO | Branch on No Output | - | - | - | - | - | - | - | - |
| BNC | Branch on Not Carry | CF | - | - | - | - | - | - | - |
| BC | Branch on Carry | CF | - | - | - | - | - | - | - |
| BGE | Branch on Greater than or Equal | - | VF⨁NF | - | - | - | - | - | |
| BLT | Branch on Less Than | - | VF⨁NF | - | - | - | - | - | |
| BGT | Branch on Greater Than | - | (VF⨁NF)∨ZF |
- | - | - | - | ||
| BLE | Branch on Less than or Equal | - | (VF⨁NF)∨ZF | - | - | - | - | ||
| ACC | IX | d | [d] | (d) | [IX+d] | (IX+d) | |
| LD ACC, | 60 | 61 | 62 | 64 | 65 | 66 | 67 |
| ST ACC, | - | - | - | 74 | 75 | 76 | 77 |
| SBC ACC, | 80 | 81 | 82 | 84 | 85 | 86 | 87 |
| ADC ACC, | 90 | 91 | 92 | 94 | 95 | 96 | 97 |
| SUB ACC, | A0 | A1 | A2 | A4 | A5 | A6 | A7 |
| ADD ACC, | B0 | B1 | B2 | B4 | B5 | B6 | B7 |
| EOR ACC, | C0 | C1 | C2 | C4 | C5 | C6 | C7 |
| OR ACC, | D0 | D1 | D2 | D4 | D5 | D6 | D7 |
| AND ACC, | E0 | E1 | E2 | E4 | E5 | E6 | E7 |
| CMP ACC, | F0 | F1 | F2 | F4 | F5 | F6 | F7 |
| ACC | IX | d | [d] | (d) | [IX+d] | (IX+d) | |
| LD IX, | 68 | 69 | 6A | 6C | 6D | 6E | 6F |
| ST IX, | - | - | - | 7C | 7D | 7E | 7F |
| SBC IX, | 88 | 89 | 8A | 8C | 8D | 8E | 8F |
| ADC IX, | 98 | 99 | 9A | 9C | 9D | 9E | 9F |
| SUB IX, | A8 | A9 | AA | AC | AD | AE | AF |
| ADD IX, | B8 | B9 | BA | BC | BD | BE | BF |
| EOR IX, | C8 | C9 | CA | CC | CD | CE | CF |
| OR IX, | D8 | D9 | DA | DC | DD | DE | DF |
| AND IX, | E8 | E9 | EA | EC | ED | EE | EF |
| CMP IX, | F8 | F9 | FA | FC | FD | FE | FF |
| ACC | IX | |
| SRA | 40 | 48 |
| SLA | 41 | 49 |
| SRL | 42 | 4A |
| SLL | 43 | 4B |
| RRA | 44 | 4C |
| RLA | 45 | 4D |
| RRL | 46 | 4E |
| RLL | 47 | 4F |
| BA | 30 |
| BVF | 38 |
| BNZ | 31 |
| BZP | 32 |
| BP | 33 |
| BNI | 34 |
| BNC | 35 |
| BGE | 36 |
| BGT | 37 |
| BZ | 39 |
| BN | 3A |
| BZN | 3B |
| BNO | 3C |
| BC | 3D |
| BLT | 3E |
| BLE | 3F |
| NOP | 00 |
| HLT | 0F |
| OUT | 10 |
| IN | 1F |
| RCF | 20 |
| SCF | 2F |
The KUE-CHIP2 educational board is very useful for understanding the operation of the processor. However, the user interface is mainly limited to a few buttons and switches and two types of 7-segment displays.
It is not easy to input programs, display data, and check program operation with such an interface. We improved this point by simulating the KUE-CHIP2 instruction set in software, and added the following functions that are difficult to realize in hardware.
The simulator is written as a Java applet. Therefore, the simulator can be used by anyone with a Java-compatible browser at any time via the Internet, independent of the user's computer environment. The simulator can be used by anyone with a Java-compatible browser, independent of the user's computer environment. In addition, because it is a Java applet, the load on a particular server can be reduced.