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Published Papers by Computer System Lab

Title First Author Date
Genetic Algorithm Approach to Scheduling Problems of the Operating Systems on Parallel Computers Hideo KAKISHIRO Dec. 1994
A Parallel Symbol Processing System on a Distributed Memory Parallel Computer Hirokazu FUKUI Dec. 1994
Message Driven Thread Architecture for Massively Parallel Computers Yukishige SHIBATA Aug. 1995
A Parallel Object Management Scheme for Massively Parallel Computers Hideaki NISHINO May 1996
Dynamic Load Balancing Scheme based on the Hierarchical Management of Overlapped Processor Region for Massively Parallel Computers Atsushi NUNOME May 1996
A Proposal of HXB/b-HC interconnection network for massively parallel computers Takeshi SHIMOMURA Aug. 1996
Speedups of an MPEG encoder by parallel processings Shuji YAMAMURA Aug. 1996
Message Driven Thread Architecture MDT-1 Yukishige SHIBATA Aug. 1996
To Speed-up Garavitational N-body Problem Solving by Parallel Processing Keizo NONAKA Mar. 1997
Studies of Hierarchical Thread Scheduling for Distributed Memory Parallel Processors Katsuhide AMATSU Jul. 1997
Performance Comparisons of Instruction Cache Configurations and Instruction Fetch Schemes for a Multithreaded Processor or a 1-Chip Multiprocessor Hiroaki HIRATA Jun. 1998
Dynamically Load Balancing Scheme Considering the Load Variation Speed for Massively Parallel Computers Atsushi NUNOME Aug. 1998
Parallel Execution of Loop Iterations by Speculative Traversal on Recursive Data Structures Toshiki MOTOKAWA Jan. 2000
A Data Prefeching Mechanism for A Linked List Structure Shuji YAMAMURA May 2000
An Evaluation of A Data Preload Mechanism for A Linked List Structure Shuji YAMAMURA Aug. 2000
Preliminary Evaluation of Data Value Prediction for A Speculative Parallel Execution of Loop Iterations Koji ADACHI Aug. 2000
Dynamic Load Balancing Scheme Considering the Load Growing Rate for Massively Parallel Computers Atsushi NUNOME Sept. 2000
An Evaluation of A Data Preload Mechanism for A Linked List Structure Shuji YAMAMURA Feb. 2001
An Improvement of Dynamic Load Balancing Scheme with Load Prediction Mechanism for Massively Parallel Computers Atsushi NUNOME May 2001
Performance Evaluation of Dynamic Load Balancing Scheme with Load Prediction Mechanism Using the Load Growing Acceleration for Massively Parallel Computers Atsushi NUNOME Nov. 2001
Design and Evaluation of the Communication Library for a Parallel Processing using the Domain Decomposition Method with Boundary Data Synchronization on PC Cluster Jinsuke NAKAI Mar. 2002
Evaluation of a Data Preload Mechanism for a Linked list Structure Shuji YAMAMURA Mar. 2002
Performance Evaluation of Dynamic Load Balancing Scheme with Load Prediction Mechanism Using the Load Growing Acceleration for Massively Parallel Computers Atsushi NUNOME Oct. 2004
An Ethernet Switch with Two-Level Broadcast Domain for Network Authentication Atsushi NUNOME Apr. 2005
Development of an E-learning Back-end System for Code Assessment in Programing Practice Atsushi NUNOME May 2008
An Attached Processor for Buffer-Overflow Detection Shohei NOMA Mar. 2009
Precise Detection of Stack-Smashing Attacks and Requirements for its Efficient Implementation Shohei NOMA Dec. 2009
Classification of Inter-Thread Dependencies for Thread-Level Parallelization Kiyotaka MORITA Sept. 2010
Performance Optimization of an Electronic Commerce Site by Database Query Scheduling Kenjirou AKASAKA Sept. 2010
Precise Detection of Procedure Calling/Returning through Machine Instruction-Level Monitoring Hiroaki HIRATA Sept. 2010
Development of an E-learning Back-end System for Code Assessment in Elementary Programming Practice Atsushi NUNOME Oct. 2010
A Multicast Filtering Ethernet Switch for Network Authentication in IPv6 Networks Atsushi NUNOME Sept. 2011
A Processor Architecture Featured with a Precise Detection Mechanism of Stack Smashing Attacks Kunio NAKATSUKASA Sept. 2011
Memory Renaming for Thread-Level Parallelization Takahiro FUJII Sept. 2011
Database Query Scheduling to Improve the Response Time in an Electronic Commerce Site Kenjirou AKASAKA Sept. 2011
A Memory Renaming Mechanism for a Thread-Level Speculation on a Multiprocessor Hiroaki HIRATA Sept. 2012
Dynamic Commutativity Analysis for a Thread-Level Speculation on a Multiprocessor Kouhei FUJI Sept. 2012
A Dynamic Path Prediction of Basic Blocks to be Executed Hiroyuki YASUI Sept. 2012
Consultation Algorithm using Recent Decision History for Computer Shogi Makoto HIDAKA Sept. 2013
The Possibility to Extract Thread-Level Parallelism from Non-Locally Nested Loops Harunobu UESUGI Sept. 2013
A Lazy-Updating Protocol of a Snoop Cache to Implement the Transactional Memory Sekai ICHII Sept. 2013
A Branch Prediction using the Colleration with Returning from a Function Yui YOSHIKAWA Sept. 2013
A Microprocessor Architecture Enhanced to Detect Return Address Corruption Kunio NAKATSUKASA Mar. 2014
A Lazy-Updating Snoop Cache Protocol for Transactional Memory Sekai ICHII Jun. 2014
A Distributed Storage System with Dynamic Tiering for iSCSI Environment Atsushi NUNOME Aug. 2014
An Information Propagation Scheme for an Autonomous Distributed Storage System in iSCSI Environment Shingo SHIMANO Jul. 2015
A Large-Scale Speculation for the Thread-Level Parallelization Yuki SHOJI Jul. 2015
Hardware Transactional Memory with Delayed Committing Sekai ICHII Jul. 2015
A Value Prediction Mechanism for a Thread-Level Speculation on a Multiprocessor Yuki SHOJI Jul. 2015
An Interval Control Method for Status Propagation in an Autonomous Distributed Storage System Atsushi NUNOME Jun. 2016
Speculative Memory: An Architectural Support for Explicit Speculations in Multithreaded Programming Hiroaki HIRATA Jun. 2016
An Analyzing Mechanism of Data Dependencies for the Thread-Level Speculation Takashi Dejima Mar. 2017
A Software Implementation of Speculative Memory Kohei FUJISAWA Jun. 2017
Performance Evaluation of Delayed-Committing Transactional Memory Sekai ICHII Jun. 2017
An Autonomous Configuration Scheme of Storage Tiers for Distributed File System (Best Student Presenter Award) Shingo SHIMANO Jun. 2017
A Dynamic Configuration Scheme of Storage Tiers for an Autonomous Distributed Storage System Shingo SHIMANO Dec. 2017
Design Space Exploration for Implementing a Software-based Speculative Memory System Kohei FUJISAWA Mar. 2018
A Data Migration Scheme Considering Node Reliability for an Autonomous Distributed Storage System (Best Paper Award) Atsushi NUNOME Jul. 2018
Parallelizing the Construction of a k-Dimensional Tree Hiroki YAMASAKI Jul. 2018
Shelving a Code Block for Thread-Level Speculation Daiki MATSUNAGA Jul. 2019
Performance Evaluation of Parallel Heapsort Programs Hikaru KITANO Jul. 2019
An Improvement of Migration Efficiency in a Distributed Storage System with Dynamic Tiering Atsushi NUNOME Jul. 2019
Performance Evaluation of Data Migration Policies for a Distributed Storage System with Dynamic Tiering Atsushi NUNOME Dec. 2019
Decoupling Computation and Result Write-Back for Thread-Level Parallelization Hiroaki HIRATA Jul. 2020
A Modified Parallel Heapsort Algorithm Hiroaki HIRATA Jul. 2020
Reducing the Repairing Penalty on Misspeculation in Thread-Level Speculation Hiroaki HIRATA Jun. 2021
An Adaptive Tiering Scheme for an Autonomous Distributed Storage System Atsushi NUNOME Jun. 2021
Parallel Binary Search Tree Construction Inspired by Thread-Level Speculation Hiroaki HIRATA Jul. 2022
Enhancing the Performance of an Autonomous Distributed Storage System in a Large-Scale Network Atsushi NUNOME Jul. 2022
Adaptive Parameter Tuning for Constructing Storage Tiers in an Autonomous Distributed Storage System Atsushi NUNOME Nov. 2022


Dec. 1, 2022